1. Field of the Invention
The invention relates to a switching circuit device and, in particular, a switching circuit device with a greatly improved electrostatic breakdown voltage.
2. Description of the Related Art
Mobile communications equipment such as portable telephones often uses GHz-band microwaves, and in their antenna switching circuits and transmitting and receiving switching circuits, etc., switching elements for switching high-frequencies thereof are often used. As an element thereof, a field-effect transistor (hereinafter referred to as a FET) using gallium arsenide (GaAs) is often employed because high frequencies are used, and accordingly, developments have been made in forming a monolithic microwave integrated circuit (MMIC) by integrating the aforementioned switching circuits themselves.
In FIG. 29A through FIG. 32C, an example of a conventional switching circuit device using GaAs FETs will be described. FIG. 29A shows an example of a theoretical circuit diagram of a compound semiconductor device using GaAs FETs, which is called an SPDT (Single Pole Double Throw).
Sources (or drains) of first and second FET1 and FET2 are connected to a common input terminal IN, and gates of the respective FET1 and FET2 are connected to first and second control terminals Ctl-1 and Ctl-2 via resistors R1 and R2, and drain (or sources) of the respective FETs are connected to first and second output terminals OUT-1 and OUT-2. Signals to be applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET to which an H-level signal has been applied is turned ON and transmit the signal applied to the input terminal IN to the corresponding output terminal. The resistors R1 and R2 are arranged for the purpose of preventing high-frequency signals from leaking via the gate electrodes to the DC potential of the control terminals Ctl-1 and Ctl-2 which are AC grounded.
FIG. 29B is a plan view of a device in which the above compound semiconductor switch circuit device is integrated.
As shown in the drawing, the FET1 and FET2 (both the gate width of 600 μm) for switching are arranged in the central parts of a GaAs substrate, and the resistors R1 and R2 are connected to gate electrodes of the respective FETs. In addition, pads I,O1, O2,C1 and C2 corresponding to the common input terminal IN, output terminals OUT-1 and OUT-2, control terminals Ctl-1 and Ctl-2 are provided at the periphery of the substrate. Moreover, second-layer wiring indicated by dotted lines is a gate metal layer (Ti/Pt/Au) 168 formed simultaneously with a gate electrode formation of the respective FETs, and third-layer wiring indicated by solid lines is a pad metal layer (Ti/Pt/Au) 177 for connection of respective elements and a pad formation. An ohmic metal layer (AuGe/Ni/Au), which is in ohmic contact with the first-layer substrate, forms source electrodes and drain electrodes of the respective FETs, and forms electrodes at both ends of the respective resistors, and is not illustrated in FIG. 29 since this overlaps with the pad metal layer.
In a part where each electrode pad and wiring are adjacent, impurity regions 160 and 161 are provided in contact with the whole lower surface or a peripheral part of the electrode pad and wiring. The impurity regions 160 and 161 are provided in a protruding manner from a contact part of the electrode pad or wiring to the substrate and secure a predetermined isolation.
In FIG. 30, a sectional view of a part of an FET of the switching circuit device of FIG. 29B is shown. FET1 and FET2 for a switching operation and FET3 and FET4 as shunt FETs are all of an identical structure, and a source electrode 175 (165), a drain electrode 176 (166), and a gate electrode 169 are arranged in the form of comb teeth in each FET, and illustrated is a set thereof.
As in FIG. 30, on the substrate 151, an operation layer 152 by an n-type ion-implanted layer and, on both sides thereof, n+-type impurity regions to form a source region 156 and a drain region 157 are provided, and on the operation layer 152, a gate electrode 169 is provided, and on the impurity regions, a drain electrode 166 and a source electrode 165 formed of the first-layer ohmic metal layer are provided. Further thereon, provided are a drain electrode 176 and a source electrode 175 formed of the third-layer pad metal layer 177 as described above, whereby wiring for the respective elements is carried out.
As shown in FIG. 30B, a MESFET as typified by the above is small in the capacity of a gate Schottky junction and is the least resistant to electrostatic breakdown when a surge voltage is applied between the gate electrode G to source electrode S or between the gate electrode G and drain electrode D, with its gate electrode G side provided as negative. In this case, static electricity is applied in a reverse-biased manner to a Schottky barrier diode 115 formed at an interface between a channel region 144 and the gate electrode 169 provided on the surface of the channel region 144. In terms of an equivalent circuit, the Schottky barrier diode 115 is connected between the gate electrode G and source electrode S and between the gate electrode G and drain electrode D.
In addition, in FIG. 31A thorough FIG. 32C, an example of a method for manufacturing FETs, pads and wiring of the switching circuit device of FIG. 29B will be shown. Although a description will be herein given of one electrode pad, electrode pads to be connected to the above-described common input terminal, first and second control terminals, and first and second output terminals are all of an identical structure.
The whole surface of a compound semiconductor substrate 151 formed of GaAs or the like is covered with a silicon nitride film 153 through ion implanting having a thickness of approximately 100 Å to 200 Å. Next, GaAs at the outermost periphery of the chip or a predetermined region of the mask is etched to form alignment marks (unillustrated), and a photolithography process is performed to selectively open windows in a resist layer, and an ion implantation of impurity (24 vig+) of p−-type and an ion implantation of impurity (29Si+) of n-type are performed. As a result, a p−-type region 155 and an n-type operation layer 152 are formed on the region 155 in an undoped substrate 151.
Next, the resist layer 154 used in the previous step is removed, a resist layer 158 is newly provided, a photolithography process is performed to selectively open windows, and an ion implantation of impurity (29Si+) of n-type is performed. Thereby, an n+-type source region 156 and drain region 157 are formed, and simultaneously, n+-type regions 160 and 161 are formed on the substrate surface under a predetermined electrode pad 170 and wiring 162. In addition, resistors R1 and R2 of a desirable pattern are also simultaneously formed (FIG. 31A).
Thereby, the wiring 162 and electrode pad 170 and the substrate 151 are separated, and no depletion layer extends to the electrode pad 170 or wiring 162, therefore, the adjacent electrode pad 170 and wiring 162 can be provided at a greatly approximated alienation distance from each other. Thereafter, a silicon nitride film 153 for annealing is deposited at approximately 500 Å, and activation annealing of the ion-implanted p−-type region, n-type operation layer and n+-type regions is performed.
Thereafter, a photolithography process is performed to selectively open windows in a new resist layer 163, the surface of the source region 156 and drain region 157 is exposed by etching the silicon nitride film at the windows, and three layers of AuGe/Ni/Au to be an ohmic metal layer 164 are evaporated in this order. Thereafter, the resist layer 163 is removed to leave, by lift-off, a first source electrode 165 and a first drain electrode 166 on the source region 156 and drain region 157 in contact. Subsequently, ohmic junctions between the first source electrode 165 and source region 156 and the first drain electrode 166 and drain region 157 are formed by an alloying heat treatment (FIG. 31B).
Next, a photolithography process is performed to selectively open windows in a new resist layer 167, the operation layer 152 in a predetermined gate electrode 169 part is exposed, the substrate 151 in predetermined wiring 162 and predetermined electrode pad 170 parts is exposed, three layers of Ti/Pt/Au are evaporated in this order (FIG. 31C), and thereafter, a gate electrode 169, a first electrode pad 170, and wiring 162 are formed by lift-off (FIG. 31D).
Furthermore, the surface of the substrate 151 is covered with a passivation film formed of a silicon nitride film, a photolithography process is performed on the passivation film to selectively open windows at contact parts with the first source electrode 165, first drain electrode 166, gate electrode 169, and first electrode pad 170, the passivation film in these parts is dry-etched, and a resist layer 171 is removed (FIG. 32A).
Next, a new resist layer 173 is applied to the whole surface of the substrate 151 for a photolithography process, and a photolithography process is performed to selectively open windows in the resist on a predetermined second source electrode 175, a second drain electrode 176, and a second electrode pad 177. Subsequently, three layers of Ti/Pt/Au to be a pad metal layer 174 as a third-layer electrode are evaporated in this order, whereby a second source electrode 175 and second drain electrode 176 and a second electrode pad 177, which are in contact with the first source electrode 165, first drain electrode 166, and first electrode pad 170, are formed (FIG. 32B). Since the other parts of the pad metal layer 174 are deposited onto the resist layer 173, the resist layer 173 is removed to leave only the second source electrode 175, second drain electrode 176, and second electrode pad 177 by lift-off, while the other parts are removed. Herein, since some wiring parts are formed by use of this pad metal layer 174, as a matter of course, the pad metal layer 174 of these wiring parts is left (FIG. 32C), as described in Japanese Patent Application Publication No. 2002-231898.
In recent years, wireless broadband in a 2.4 GHz-band has shown a great expansion. Its transmitting rate is 11 Mbps, which is much greater than the transmitting rate of mobile telephones, and has become popular in ordinary households, for example, ADSL over telephone lines provides wireless service throughout an entire household, or where signals are wirelessly distributed to a cordless liquid crystal television. Recently, a 5 GHz-band has received a special attention as a next-generation wireless broadband, and furthermore, it is anticipated that its outdoor use will soon be approved as a result of a revised legislation and its range of application will be greatly expanded. Compared to the 2.4 GHz band, since the 5 GHz band enables transmitting a larger amount of information at a transmitting rate of 54 Mbps, there is great expectation for sending high-precision moving images without compression, etc., and development of apparatuses and construction of networks for that purpose have been eagerly carried out.
In 5 GHz-band broad band apparatuses, similar to those with a 2.4 GHz band, GaAs switch ICs are used for input/output switching and antenna switching. Since the frequency is twice higher than 2.4 GHz, parasitic capacitance greatly influences deterioration in isolation. As a countermeasure, a means for improving isolation has became indispensable, such as, in a circuit using shunt FETs which have not been used in a 2.4 GHz-band switch IC, for releasing signals leaked to its OFF-side FET to its high frequency GND.
However, since these shunt FETs are narrow in the gate width, they tend to have a low electrostatic breakdown voltage because of small parasitic capacitance.